1. Field of the Invention
The present invention relates to a quadrature demodulation circuit used for digital television broadcasting.
2. Description of Related Art
The technology for supplying digital television broadcasting signals having been practically implemented, commercial digital television broadcasting has begun. Commercial digital television broadcasting can be broadly divided into either broadcasting where digital television signals are transmitted by satellite or broadcasting using terrestrial waves. In the following, satellite digital television broadcasting will be described.
FIG. 5 illustrates a structure of one frame of digital data to be received in a satellite digital broadcasting receiver. One frame of digital data as depicted in FIG. 5 contains 39936 symbols, a symbol as used herein referring to a signal received in synchronization with one clock. The leading end portion of one frame includes a transmission multiple control (TMCC) signal for transmitting control information regarding a slot signal or a transmission system, and a synchronization word signal. The synchronization word signal contains a total of 40 symbols, while the number of symbols in the TMCC and synchronizing word signals totals 192, which are to be transmitted as a BPSK (binary PSK) modulation signal.
After the TMCC signal and the synchronization word signal, data (containing separate tracks such as video, audio, or the like) and carrier clock burst signals are alternately provided. Each data portion contains 203 symbols and each carrier clock burst signal contains 4 symbols. A carrier clock burst signal is a BPSK modulation signal.
A data portion containing 203 symbols and a carrier clock burst signal portion containing 4 symbols constitute one set of data, and 4 sets in succession, ((203+4)xc3x974) symbols, is referred to as one xe2x80x9cslotxe2x80x9d.
Slots are modulated using different types of modulation. The type of modulation used and the order of data transmission are recognized after drawing frequency of the carrier clock has been determined, by detecting a synchronization word, establishing a frame synchronization, and demodulating the TMCC. The modulation types to be used include 8PSK, QPSK (Quadrature PSK), BPSK, or the like.
FIG. 6 illustrates a structure of a satellite digital broadcasting receiver. A digital television signal transmitted from a satellite is received by a tuner 61 where synchronous detection is applied while the frequency is down-converted. A digital modulation signal obtained from the tuner 61 is demodulated in a quadrature demodulation circuit 62 to produce I and Q baseband signals. A PSK demodulation circuit 63 provides various types of PSK demodulation according to the I and Q baseband signals, and an error correction circuit 64 applies error correction to a PSK demodulation signal. The PSK demodulation signal subjected to error correction is decoded into motion image data or audio data in a signal processing circuit 65 according to set protocols such as those of the MPEG1 or MPEG2 system.
FIG. 3 illustrates an example of a quadrature demodulation circuit 62. Multipliers 1 and 2 constituting a quasi synchronous detector applies synchronous detection to a digital television signal to output I and Q signals, which are then converted by AD converters 3 and 4 into digital data and input into a demodulator 5.
The demodulator 5 corrects the I and Q signals such that their vectors enter an ideal state and outputs I and Q baseband signals. The I baseband signal is input to a clock reproduction circuit 6 which reproduces a reproduction clock CK synchronized with the baseband signal by a PLL method. In the clock reproduction circuit 6, a zero crossing point of the baseband signal serving as a reference signal is detected as shown in FIG. 2A, and the frequency of a VOC in the clock reproduction circuit 6 is controlled such that the phase of the zero crossing point and the phase of a rising edge of the reproduction clock CK are synchronized. FIG. 2A indicates that phase synchronization is established between a baseband signal and a reproduction clock.
The AD converters 3 and 4 may output a digital data superposed with a DC offset depending on their performance, and this causes the following problems.
FIG. 4 illustrates a constellation of the QPSK modulation system. In the QPSK system, each point (A, B, C, D) representing a vector of a baseband signal appears in each of four quadrants and the vectors can transit between the points according to data. When a DC offset exists in the AD converters 3 and 4, the vector of a baseband signal does not represent an ideal state by indicating a wrong point according to the amplitude level of the baseband signal. When an offset is generated in the Q baseband signal, for example, an ideal point ∘, is shifted to a point xe2x97xaf. For example, the vector of a baseband signal may be shifted to a point Axe2x80x2 depending on DC offset. In this case, it is probable that a baseband signal which should be demodulated as a point A may be incorrectly demodulated as a point B depending on the amplitude level of the offset. If the distance between each point on the constellation shown in FIG. 4 is shortened, namely if the distance between each point in a case where a DC offset exists (Axe2x80x2-Bxe2x80x2, for example) is shorter than that in a case where no DC offset exists (A-B), the noise margin with regard to noise generated in a transmission path is decreased, causing deterioration of a demodulation performance (bit error rate).
In the related art example shown in FIG. 3, in order to cancel a DC offset, a low pass filter for detecting a DC offset and an adder for removing a DC offset are provided between each of the AD converter 3 and 4 and the demodulator 5. Specifically, output data from each AD converter 3, 4 is planarized in each low pass filter to detect a DC offset, which is resultantly cancelled in the adders by subtracting the DC offset.
Such a low pass filter, however, requires a large time constant to detect the DC level, which results in a problem that the circuit scale of the low pass filter is extremely enlarged. Further, it is necessary to operate the low pass filters at a high speed with the same clock as the AD converters 3 and 4 because the low pass filters are coupled after the AD converters 3 and 4, respectively. Although a high speed operation of a large scale circuit such as the low pass filter described above can be implemented using pipeline signal processing, such a pipeline system requires that an additional register be provided.
The present invention aims to provided a device for effectively canceling a DC offset in a baseband signal.
According to an aspect of the present invention, a DC offset is detected using phase comparison results in a PLL for generating a reproduction clock synchronized with a baseband signal. Thus, it is possible to cancel a DC offset existing in a baseband signal with a simple circuit structure.
A reproduction clock synchronized with a baseband signal is necessary in a demodulation circuit. Because the PLL which generates the reproduction clock is also utilized to detect a DC offset, an extremely simple structure can be used for effective DC offset detection.